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CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9
Integrated Device Technology, Inc.
IDT72131 IDT72141
FEATURES:
* 35ns parallel port access time, 45ns cycle time * 50MHz serial port shift rate * Expandable in depth and width with no external components * Programmable word lengths including 7-9, 16-18, 32-36 bit using FlexishiftTM serial output without using any additional components * Multiple status flags: Full, Almost-Full (1/8 from full), Half-Full, Almost Empty (1/8 from empty), and Empty * Asynchronous and simultaneous read and write operations * Dual-Port zero fall-through architecture * Retransmit capability in single device mode * Produced with high-performance, low power CMOS technology * Available in 28-pin plastic DIP * Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72131/72141 are high-speed, low power parallelto-serial FIFOs. These FIFOs are ideally suited to serial communications applications, tape/disk controllers, and local area networks (LANs). The IDT72131/72141 can be configured with the IDTs serial-to-parallel FIFOs (IDT72132/72142) for bidirectional serial data buffering. The FIFO has a 9-bit parallel input port and a serial output port. Wider and deeper parallel-to-serial data buffers can be built using multiple IDT72131/72141 chips. IDTs unique Flexishift serial expansion logic (SOX, NR) makes width expansion possible with no additional components. These FIFOs will expand to a variety of word widths including 8, 9, 16, and 32 bits. The IDT72131/141 can also be directly connected for depth expansion. Five flags are provided to monitor the FIFO. The full and empty flags prevent any FIFO data overflow or underflow conditions. The almost-full (7/8), half-full, and almost empty (1/8) flags signal memory utilization within the FIFO. The IDT72131/72141 is fabricated using IDTs high-speed submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
D0-D 8
PIN CONFIGURATION
W
D4 D3 D2 D1
NEXT READ POINTER NR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24
Vcc D5 D6 D7 D8
EF FLAG LOGIC AEF /HF FF WRITE POINTER RAM ARRAY 2048 x 9 4096 x 9
W
D0
XI
SOX SOCP SO
P28-1 & C28-3
23 22 21 20 19 18 17 16 15
FL/RT RS EF XO/HF
GND Q8 Q7 Q6
RS FL/RT
RESET LOGIC SOCP EXPANSION LOGIC SERIAL OUTPUT CIRCUITRY SOX SO
AEF FF
Q4 GND
XI
XO/
NR
Q4 Q6 Q7 Q8
2751 drw 01
DIP TOP VIEW
2751 drw 02a
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2751/6
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol D0-D8 Inputs Reset Name I/O I I Data inputs for 9-bit wide data. When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM array. HF and FF go HIGH, and AEF and EF go LOW. A reset is required before an initial WRITE after power-up. W must be HIGH and SOCP must be LOW during RS cycle. A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data setup and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation. A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together. To program the Serial Out data word width , connect NR with one of the Data Set pins (Q4, Q6, Q7 and Q8). For example, NR - Q7 programs for a 8-bit Serial Out word width. This is a dual purpose input. In the single device configuration (XI grounded), activating retransmit (FL/RT-LOW) will set the internal READ pointer to the first location. There is no effect on the WRITE pointer. W must be high and SOCP must be low before setting FL/RT LOW. Retransmit is not compatible with depth expansion. In the depth expansion configuration, FL/RT grounded indicates the first activated device. In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion, XI is connected to XO (expansion out) of the previous device. In the Serial Output Expansion mode, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other devices is connected to the Q8 pin of the previous device. Data is then clocked out least significant bit first. For single device operation, SOX is tied HIGH. Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first. In the Serial Width Expansion mode the SO pins are tied together and each SO pin is tristated at the end of the byte. When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH, the device is not full. When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the device is not empty. See the description on page 6 for more details. When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH, the device is greater than 1/8 full, but less than 7/8 full. This is a dual-purpose output. In the single device configuration (XI grounded), the device is more than half full when HF is LOW. In the depth expansion configuration (XO connected to XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array is filled. Description
RS W
SOCP
Write
I
NR FL/RT
Serial Output Clock Next Read First Load/ Retransmit
I I I
XI
SOX
Expansion In Serial Output Expansion
I I
SO
Serial Output
O
FF EF AEF XO/HF
Q4, Q6, Q7 and Q8 VCC GND
Full Flag Empty Flag Almost-Empty/ Almost-Full Flag Expansion Out/ Half-Full Flag Data Set
O O O O
O
The appropriate Data Set pin (Q4, Q6, Q7 and Q8) is connected to NR to program the Serial Out data word width. For example: Q6 - NR programs a 7-bit word width, Q8 - NR programs a 9-bit word width, etc. Single Power Supply of 5V. Single ground at 0V.
Power Supply Ground
2751 tbl 01
STATUS FLAGS
Number of Words in FIFO IDT72131 0 1-255 256-1024 1025-1792 1793-2047 2048 IDT72141 0 1-511 512-2048 2049-3584 3585-4095 4096
FF
H H H H H L
AEF
L L H H L L
HF
H H H L L L
EF
L H H H H H
2751 tbl 02
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 Unit V
RECOMMENDED OPERATING CONDITIONS
Symbol VCC GND VIH VIL(1) Parameter Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input Low Voltage Min. 4.5 0 2.0 -- Typ. 5.0 0 -- -- Max. Unit 5.5 0 -- 0.8 V V V V
2751 tbl 04
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
C C C mA
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
NOTE: 2751 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 12 Unit pF pF
2751 tbl 05
NOTE: 1. This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C
IDT72131/IDT72141 Commercial Symbol IIL
(1)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage, IOUT = -8mA Output Logic "0" Voltage IOUT = 16mA Power Supply Current Average Standby Current (W = RS = FL/RT = VIH) (SOCP = VIL) Power Down Current
Min. -1 -10 2.4 -- -- --
Typ. -- -- -- -- 90 8
Max. 1 10 -- 0.4 140 12
Unit A A V V mA mA
IOL(2) VOH VOL ICC1(3) ICC2
(3)
ICC3(L)(3,4)
--
--
2
mA
2751 tbl 06
NOTES: 1. Measurements with 0.4 VIN VCC. 2. SOCP VIL, 0.4 VOUT VCC. 3. ICC measurements are made with outputs open. 4. RS = FL/RT = W = VCC -0.2V; SOCP 0.2V; all other inputs VCC -0.2V or 0.2V.
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C)
Commercial IDT72131L35 IDT72141L35 Min. Max. -- -- 18 0 45 35 10 -- -- -- 35 5 5 -- 5 8 -- -- -- 35 45 35 35 10 -- -- 20 20 45 35 35 10 -- -- 35 10 15 22.2 50 -- -- -- -- -- 30 30 45 -- 16 22 18 -- -- 20 30 30 -- -- -- -- -- 45 45 -- -- -- -- -- -- 35 35 -- -- -- IDT72131L50 IDT72141L50 Min. Max. -- -- 30 5 65 50 15 -- -- -- 50 5 5 -- 5 10 -- -- -- 50 65 50 50 15 -- -- 35 35 65 50 50 15 -- -- 50 10 15 15 40 -- -- -- -- -- 45 45 65 -- 26 22 18 -- -- 25 40 40 -- -- -- -- -- 65 65 -- -- -- -- -- -- 50 50 -- -- --
Symbol tS tSOCP tDS tDH tWC tWPW tWR tWEF tWFF tWF tWPF tSOHZ tSOLZ tSOPD tSOX tSOCW tSOCEF tSOCFF tSOCF tREFSO tRSC tRS tRSS tRSR tRSF1 tRSF2 tRSQL tRSQH tRTC tRT tRTS tRTR tXOL tXOH tXI tXIR tXIS
Parameter Parallel Shift Frequency Serial-Out Shift Frequency Data Set-up Time Data Hold Time Write Cycle Time Write Pulse Width Write Recovery Time Write High to EF HIGH Write Low to FF LOW Write Low to Transitioning HF, AEF Write Pulse Width After FF HIGH
Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2751 tbl 07
PARALLEL INPUT TIMINGS
SERIAL OUTPUT TIMINGS SOCP Rising Edge to SO at High-Z(1) SOCP Rising Edge to SO at Low-Z(1) SOCP Rising Edge to Valid Data on SO SOX Set-up Time to SOCP Rising Edge Serial In Clock Width HIGH/LOW SOCP Rising Edge (Bit 0 - Last Word) to EF LOW SOCP Rising Edge to FF HIGH SOCP Rising Edge to HF, AEF, HIGH Recovery Time SOCP After EF HIGH Reset Cycle Time Reset Pulse Width Reset Set-up Time Reset Recovery Time Reset to EF and AEF LOW Reset to HF and FF HIGH Reset to Q LOW Reset to Q HIGH Retransmit Cycle Time Retransmit Pulse Width Retransmit Set-up Time Retransmit Recovery Time Read/Write to XO LOW
RESET TIMINGS
RETRANSMIT TIMINGS
DEPTH EXPANSION MODE TIMINGS Read/Write to XO HIGH
XI Pulse Width XI Recovery Time XI Set-up Time
NOTE: 1. Guaranteed by design minimum times, not tested.
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure A
2751 tbl 08
5V
1.1K D.U.T. 680 30pF*
2751 drw 03
or equivalent circuit
Figure A. Ouput Load *Including jig and scope capacitances
FUNCTIONAL DESCRIPTION
Parallel Data Input The data is written into the FIFO in parallel through the D0-8 input data lines. A write cycle is initiated on the falling edge of the Write (W) signal provided the Full Flag (FF) is not asserted. If the W signal changes from HIGH-to-LOW and the Full-Flag (FF) is already set, the write line is inhibited internally from incrementing the write pointer and no write operation occurs. Data set-up and hold times must be met with respect to the rising edge of Write. The data is written to the RAM at the write pointer. On the rising edge of W, the write pointer is incremented. Write operations can occur simultaneously or asynchronously with read operations.
Serial Data Output The serial data is output on the SO pin. The data is clocked out on the rising edge of SOCP providing the Empty Flag (EF) is not asserted. If the Empty Flag is asserted then the next data word is inhibited from moving to the output register and being clocked out by SOCP. NOTE: SOCP should not be clocked once the last bit of the last word has been clocked out. If it is, then two things will occur. One, the SO pin will go High-Z and two, SOCP will be out of sync with Next Read (NR). The serial word is shifted out Least Significant Bit first, that is the first bit will be D0, then D1 and so on up to the serial word width. The serial word width must be programmed by connecting the appropriate Data Set line (Q4, Q6, Q7 or Q8) to the NR input. The Data Set lines are taps off a digital delay line. Selecting one of these taps, programs the width of the serial word to be read and shifted out.
tRSC tRS RS tRSS W tRSF1 AEF, EF tRSF2 HF, FF tRSS SOCP tRSQL Q4, Q6, Q7, Q8
2751 drw 04
tRSR
tRSR
tRSQH
Figure 1. Reset
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
tWC W t WPW D0-8 tDS
Figure 2. Write Operation
tWR
tDH
2751 drw 05
1/f SOCP
0 1 n-1
SOCP t SOCW SOX t SOX SO (1) t SOHZ SO
(2)
t SOCW
t SOLZ t SOPD
Figure 3. Read Operation NOTES: 1. This timing applies to the Active Device in Width Expansion Mode. 2. This timing applies to Single Device Mode at Empty Boundary (EF = LOW) and the Next Active Device in Width Expansion Mode.
2751 drw 06
LAST WRITE
IGNORED WRITE
0
FIRST READ
1 n-1 0
ADDITIONAL READS
1 n-1
FIRST WRITE
SOCP
W t WFF FF
Figure 4. Full Flag from Last Write to First Read
2751 drw 07
t SOCFF
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
LAST READ W
0 1 n-1
NO READ
FIRST WRITE
ADDITIONAL WRITES
FIRST READ
0 (1)
1
n-1
SOCP tSOCEF EF t SOPD SO VALID
t WEF
VALID
2751 drw 08
NOTE: 1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH. Figure 5. Empty Flag from Last Read to First Write
DATA IN
W t WEF EF t REFSO SOCP
(1) 0 1 n-1
t SOCEF
t SOLZ SO t SOPD
NOTE: 1. SOCP should not be clocked until EF goes HIGH. Figure 6. Empty Boundary Condition Timing
2751 drw 09
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
0 1 n-1
COMMERCIAL TEMPERATURE RANGES
SOCP t SOCFF FF t WPF W t DS DATA IN tSOPD SO DATA OUT VALID
2751 drw 10
t WFF
t DH
DATA IN VALID
Figure 7. Full Boundry Condition Timing
W HALF-FULL (1/2) HF t WF SOCP t WF AEF 7/8 FULL ALMOST FULL (7/8 FULL + 1) 1/8 FULL tSOCF 7/8 FULL HALF-FULL +1 tSOCF HALF-FULL
AEF
ALMOST-EMPTY (1/8 FULL-1)
ALMOST-EMPTY (1/8 FULL-1)
2751 drw 11
Figure 8. Half Full, Almost Full and Almost Empty Timings
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
tRTC t RT RT tRTS SOCP tRTR 0 1
W tRTS EF, AEF, HF, FF
NOTE: 1. EF, AEF, HF and FF may change status during Retransmit, but flags will be valid at tRTC. Figure 9. Retransmit
FLAG VALID
2751 drw 12
WRITE TO LAST PHYSICAL LOCATION W LAST -1
0
READ FROM LAST PHYSICAL LOCATION LAST
1 0 1
SOCP t XOL XO
2751 drw 13
t XOH
t XOL
t XOH
Figure 10. Expansion-Out
tXI XI t XIS W Write to first physical location
t XIR
t XIS SOCP
Read from first physical location
2751 drw 14
Figure 11. Expansion-In
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Single Device Configuration In the standalone case, the SOX line is tied HIGH and not used. On the first LOW-to-HIGH of the SOCP clock, all of the
Data Set lines (Q4, Q6, Q7, Q8) go LOW and a new serial word is started. The Data Set lines then go HIGH on the equivalent SOCP clock pulse. This continues until the Q line connected to NR goes HIGH completing the serial word. The cycle is then repeated with the next LOW-to-HIGH transition of SOCP.
PARALLEL DATA IN D 0-7 SERIAL OUTPUT CLOCK VCC SOCP SOX NR Q4 Q 6 Q 7 Q8 SO XI SERIAL DATA OUTPUT GND
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
SOCP
Q4
Q6
Q7
NR
2751 drw 15
Figure 12. Eight-Bit Word Single Device Configuration
TRUTH TABLES TABLE 1: RESET AND RETRANSMIT -- SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Mode Reset Retransmit Read/Write Internal Status Outputs
RS
0 1 1
FL/RT
X 0 1
XI
0 0 0
Read Pointer Location Zero Location Zero Increment(1)
Write Pointer Location Zero Unchanged Increment(1)
AEF, EF
0 X X
FF
1 X X
HF
1 X X
2751 tbl 09
NOTE: 1. Pointer will increment if appropriate flag is HIGH.
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration In the cascaded case, word widths of more than 9 bits can be achieved by using more than one device. By tying the SOX line of the least significant device HIGH and the SOX of the subsequent devices to the appropriate Data Set lines of the previous devices, a cascaded serial word is achieved. On the first LOW-to-HIGH clock edge of SOCP, all lines go LOW. Just as in the standalone case, on each corresponding clock cycle, the equivalent Data Set line goes HIGH in order of least to most significant. When the Data Set line which is
connected to the SOX input of the next device goes HIGH, the D0 of that device goes HIGH, the cascading from one device to the next. The Data Set line of the most significant bit programs the serial word width by being connected to all NR inputs. The Serial Data Output (SO) of each device in the serial word must be tied together. Since the SO pin is three stated, only the device which is currently shifting out is enabled and driving the 1-bit-bus.
PARALLEL DATA IN 16-BITS WIDE
9
GND
SERIAL DATA OUTPUT SO SOCP SOX
7
GND
SO SERIAL OUTPUT CLOCK VCC SOCP SOX
D 0-8
XI FIFO #1
D 0-6
XI FIFO #2
NR
Q8
NR
Q6
0
1
7
8
9
10
14
15
0
SOCP Q 8 OF FIFO #1 AND SOX OF FIFO #2 Q6 OF FIFO #2 AND NR OF FIFO #1 AND FIFO #2
2751 drw 16
Figure 13. Width Wxpansion for 16-bit Parallel Data In. The Parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2.
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode The IDT72131/41 can be easily adapted to applications where the requirements are for greater than 2048/4096 words. Figure 14 demonstrates Depth Expansion using three IDT72131/41. Any depth can be attained by adding additional IDT72131/41 operates in the Depth Expansion configuration when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the OR-ing of all EFs and OR-ing of all FFs (i.e., all must be set to generate the correct composite FF or EF). 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion mode.
D 0-7
FL/RT
XI FIFO #1 IDT72141 SO SOCP XO
D 0-7 W Q7 NR W
SOX
CC V
SOCP VCC FL/RT SOX V CC SO VCC FL/RT SOX V CC
2751 drw 17
XI FIFO #2 IDT72141 SO SOCP XO
D 0-7 W Q7 NR
XI FIFO #3 IDT72141 SO SOCP XO
D 0-7 W Q7 NR
Figure 14. A 12K x 8 Parallel-In Serial-Out FIFO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLE -- DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Mode Reset-First Device Reset-All Other Devices Read/Write Internal Status Outputs
RS
0 0 1
FL
0 1 X
XI
(1) (1) (1)
Read Pointer Location Zero Location Zero X
Write Pointer Location Zero Location Zero X
EF
0 0 X
FF
1 1 X
2751 tbl 10
NOTES: 1. XI is connected to XO of previous device. 2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output, XI = Expansion Input.
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IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type X Power XXX Speed X Package X Process/ Temperature Range
Blank
Commercial (0C to +70C)
P
Plastic DIP
35 50
(50MHz serial shift rate) (40MHz serial shift rate)
Parallel Access Time (tA )
L 72131 72141
Low Power 2048 x 9-Bit Parallel-Serial FIFO 4096 x 9-Bit Parallel-Serial FIFO
2751 drw 18
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